Interact with design team with purpose to solve problems and propose physical design engineering ideas.
Coordinate all timing budgeting required for physical design task.
Develop bottoms-up elements for chip design inclusive but not restricted to FET, cell as well as block-level custom layouts.
Prepare FUB-level plus Fullchip floor plans and stimulate schematic-to-layout verification as well as debug.
Analyze independently and plan all complex layout tasks related to design ECO technology limitations and project milestone requirements and deliver on time.
Prepare physical design procedures or guidelines along with BKMs on basis of understanding of advanced CMOS process technology as well as circuit requirements.
Enforce RTL-to-layout synthesis plus place and route flows.
Ensure to perform all cleanup required.
Collaborate with Design Automation (DA) teams plus design engineers to conduct problem exploration.
Evaluate options for feasibility studies and establish and execute recommendations.
Provide optimized physical design procedures for new technology.
Ensure to streamline work enabling high productivity as well as efficiency for organization.
Develop code and maintain physical design layout automation features along with macros in layout entry tools to enhance layout productivity.